1. Field of the Invention
The present invention relates to a semiconductor device having a transistor and a method for manufacturing the same.
2. Related Art
The processing utilizing plasma is often employed in processes for manufacturing semiconductor devices including a metal oxide semiconductor field effect transistor (MOSFET) and a complementary metal oxide semiconductor (CMOS). In such manufacturing process utilizing plasma, electric charge may be accumulated within an interconnect layer that is electrically coupled to a gate electrode of a MOSFET disposed on a silicon substrate. This phenomenon is referred to as an antenna effect. Electrical current potential of the interconnect layer is increased due to the accumulation of electric charge, and an electric charge flows to the silicon substrate from the interconnect layer when the increased electric potential exceeds a breakdown voltage for a gate insulator. The gate insulator is damaged in this occasion. When gate insulator is damaged, a leakage current from the gate electrode to the semiconductor substrate is increased, thereby causing a malfunction and reduced reliability of the transistor.
Known techniques for inhibiting the antenna effect include a technique disclosed in Japanese Patent Laid-Open No. 2000-323,582. The semiconductor device disclosed in Japanese Patent Laid-Open No. 2000-323,582 comprises an interconnect layer electrically coupled to an electric input unit of a gate electrode of MOSFET and a diode having a PN junction between semiconductor regions in a substrate. It is described therein that upon having such configuration, charge-up can be avoided.
Also, G. Cellere et al. propose a technique for inhibiting the plasma damage by devising the process for manufacturing the semiconductor device in “Influence of process parameters on plasma damage during inter-metal dielectric deposition”, Microelectronic Engineering, Vol. 71, 2004, pp. 133–138.